`timescale 1ns/1ns
module tb_ctrl_center();
reg sys_clk;
reg sys_rst_n;
wire [15:0] ctrl_bus;
wire [15:0] addr_bus;
wire [15:0] data_bus;
wire [15:0] ctrl_sig_inner;
wire [15:0] addr_sig_inner;
wire [15:0] data_sig_inner;
wire work_ok;

reg [15:0] cnt;
reg [15:0] test_ctrl_bus;
reg [15:0] test_addr_bus;
reg [15:0] test_data_bus;

wire [15:0] data_reg;
wire new_task;
wire wr_en;
wire rd_en;
wire [15:0] data_rw;
wire [3:0] reg_id;
wire [3:0] this_reg_id;
wire [15:0] inner_reg3;
wire [15:0] inner_reg2;
wire [15:0] inner_reg1;
wire [15:0] inner_reg0;
wire [15:0] data_out;

assign ctrl_bus = test_ctrl_bus;
assign addr_bus = test_addr_bus;
assign data_bus = test_data_bus;
assign data_reg = ctrl_center_inst.rw_reg_inst.reg_03.data_reg;
assign new_task = ctrl_center_inst.new_task;
assign wr_en = ctrl_center_inst.rw_reg_inst.reg_03.ctrl_sig_inner[0];
assign rd_en = ctrl_center_inst.rw_reg_inst.reg_03.ctrl_sig_inner[1];
assign data_rw = ctrl_center_inst.rw_reg_inst.reg_03.data_sig_inner;
assign reg_id = ctrl_center_inst.rw_reg_inst.reg_03.addr_sig_inner[3:0];
assign this_reg_id = ctrl_center_inst.rw_reg_inst.reg_03.reg_id;
assign inner_reg3 = ctrl_center_inst.inner_reg[3];
assign inner_reg2 = ctrl_center_inst.inner_reg[2];
assign inner_reg1 = ctrl_center_inst.inner_reg[1];
assign inner_reg0 = ctrl_center_inst.inner_reg[0];
assign data_out = ctrl_center_inst.rw_ram_inst.data_out;

always #10 sys_clk = ~sys_clk;

initial
begin
	sys_clk = 1'b1;
	sys_rst_n <= 1'b0;
#60
	sys_rst_n <= 1'b1;
end

always @(posedge sys_clk or negedge sys_rst_n)
	if (sys_rst_n == 1'b0)
		cnt <= 10'd0;
	else if (cnt < 16'hE000)
		cnt <= cnt + 10'd1;
	else
		cnt <= cnt;

always @(posedge sys_clk or negedge sys_rst_n)
	if (sys_rst_n == 1'b0)
	begin
		test_ctrl_bus <= 16'hz;
		test_addr_bus <= 16'hz;
		test_data_bus <= 16'hz;
	end
	
	
	else if (cnt == 16'd2)
	begin
		test_ctrl_bus <= 16'hffff;
		test_addr_bus <= 16'hz;
		test_data_bus <= 16'h0;
	end
	else if (cnt == 16'd3)		//将一个立即数1600
	begin						//写入0号内部寄存器
		test_ctrl_bus <= 16'h0010;
		test_addr_bus <= 16'hz;
		test_data_bus <= 16'd6;
	end
	else if (cnt == 16'd12)
	begin
		test_ctrl_bus <= 16'hffff;
		test_addr_bus <= 16'h0;
		test_data_bus <= 16'h0;
	end
	else if (cnt == 16'd13)		//将0号内部寄存器数据
	begin						//写入3号通用寄存器
		test_ctrl_bus <= 16'h0000;
		test_addr_bus <= 16'd3;
		test_data_bus <= 16'd0;
	end
	else if (cnt == 16'd22)
	begin
		test_ctrl_bus <= 16'hffff;
		test_addr_bus <= 16'h0;
		test_data_bus <= 16'h0;
	end
	else if (cnt == 16'd23)		//将数据从3号通用寄存器
	begin						//读入内部2号寄存器
		test_ctrl_bus <= 16'h0006;
		test_addr_bus <= 16'd3;
		test_data_bus <= 16'd0;
	end
	else if (cnt == 16'd32)
	begin
		test_ctrl_bus <= 16'hffff;
		test_addr_bus <= 16'h0;
		test_data_bus <= 16'h0;
	end
	else if (cnt == 16'd33)		//将数据从内部2号寄存器
	begin						//写入30号ram地址
		test_ctrl_bus <= 16'h000A;
		test_addr_bus <= 16'd30;
		test_data_bus <= 16'd0;
	end
	else if (cnt == 16'd42)
	begin
		test_ctrl_bus <= 16'hffff;
		test_addr_bus <= 16'h0;
		test_data_bus <= 16'h0;
	end
	else if (cnt == 16'd43)		//将数据从30号ram地址
	begin						//读入内部1号寄存器
		test_ctrl_bus <= 16'h000D;
		test_addr_bus <= 16'd30;
		test_data_bus <= 16'd0;
	end
	else if (cnt == 16'd52)
	begin
		test_ctrl_bus <= 16'hffff;
		test_addr_bus <= 16'h0;
		test_data_bus <= 16'hz;
	end
	else if (cnt == 16'd53)
	begin
		test_ctrl_bus <= 10'd21;
		test_addr_bus <= 16'h0;
		test_data_bus <= 16'hz;
	end
	else if (cnt == 16'd62)
	begin
		test_ctrl_bus <= 16'hffff;
		test_addr_bus <= 16'h0;
		test_data_bus <= 16'hz;
	end
	else if (cnt == 16'd63)
	begin
		test_ctrl_bus <= 10'd21;
		test_addr_bus <= 16'h1;
		test_data_bus <= 16'hz;
	end
	else if (cnt == 16'd72)
	begin
		test_ctrl_bus <= 16'hffff;
		test_addr_bus <= 16'h0;
		test_data_bus <= 16'hz;
	end
	else if (cnt == 16'd73)
	begin
		test_ctrl_bus <= 10'd21;
		test_addr_bus <= 16'h2;
		test_data_bus <= 16'hz;
	end
	else if (cnt == 16'd82)
	begin
		test_ctrl_bus <= 16'hffff;
		test_addr_bus <= 16'h0;
		test_data_bus <= 16'hz;
	end
	else if (cnt == 16'd83)
	begin
		test_ctrl_bus <= 10'd21;
		test_addr_bus <= 16'h3;
		test_data_bus <= 16'hz;
	end
	else if (cnt == 16'd92)
	begin
		test_ctrl_bus <= 16'hffff;
		test_addr_bus <= 16'h0;
		test_data_bus <= 16'hz;
	end
	else if (cnt == 16'd93)
	begin
		test_ctrl_bus <= 10'd21;
		test_addr_bus <= 16'h4;
		test_data_bus <= 16'hz;
	end
	else if (cnt == 16'd102)
	begin
		test_ctrl_bus <= 16'hffff;
		test_addr_bus <= 16'h0;
		test_data_bus <= 16'hz;
	end
	else if (cnt == 16'd103)
	begin
		test_ctrl_bus <= 10'd21;
		test_addr_bus <= 16'h5;
		test_data_bus <= 16'hz;
	end
	else if (cnt == 16'd112)
	begin
		test_ctrl_bus <= 16'hffff;
		test_addr_bus <= 16'h0;
		test_data_bus <= 16'hz;
	end
	else if (cnt == 16'd113)
	begin
		test_ctrl_bus <= 10'd21;
		test_addr_bus <= 16'h6;
		test_data_bus <= 16'hz;
	end
	else if (cnt == 16'd122)
	begin
		test_ctrl_bus <= 16'hffff;
		test_addr_bus <= 16'h0;
		test_data_bus <= 16'hz;
	end
	else if (cnt == 16'd123)
	begin
		test_ctrl_bus <= 10'd21;
		test_addr_bus <= 16'h7;
		test_data_bus <= 16'hz;
	end
	else if (cnt == 16'd132)
	begin
		test_ctrl_bus <= 16'hffff;
		test_addr_bus <= 16'h0;
		test_data_bus <= 16'hz;
	end
	else if (cnt == 16'd133)
	begin
		test_ctrl_bus <= 10'd21;
		test_addr_bus <= 16'h8;
		test_data_bus <= 16'hz;
	end
	else if (cnt == 16'd142)
	begin
		test_ctrl_bus <= 16'hffff;
		test_addr_bus <= 16'h0;
		test_data_bus <= 16'hz;
	end
	else if (cnt == 16'd143)
	begin
		test_ctrl_bus <= 10'd21;
		test_addr_bus <= 16'h9;
		test_data_bus <= 16'hz;
	end
	else if (cnt == 16'd152)
	begin
		test_ctrl_bus <= 16'hffff;
		test_addr_bus <= 16'h0;
		test_data_bus <= 16'hz;
	end
	else if (cnt == 16'd153)
	begin
		test_ctrl_bus <= 10'd21;
		test_addr_bus <= 16'hA;
		test_data_bus <= 16'hz;
	end

	
	
	
	else
	begin
		test_ctrl_bus <= 16'hz;
		test_addr_bus <= 16'hz;
		test_data_bus <= 16'hz;
	end

ctrl_center ctrl_center_inst
(
	.sys_clk(sys_clk),
	.sys_rst_n(sys_rst_n),
	
	.ctrl_bus(ctrl_bus),
	.addr_bus(addr_bus),
	.data_bus(data_bus),
	.ctrl_sig_inner(ctrl_sig_inner),
	.addr_sig_inner(addr_sig_inner),
	.data_sig_inner(data_sig_inner),	
	.work_ok(work_ok)
);

endmodule